The present invention, in general, relates to an address buffer for a semiconductor memory and specifically, to a CMOS address latch circuit which is compatible with low level bipolar polar voltage levels, such as TTL.
Latching buffer circuits are well known in the prior art and serve to provide buffering between a computer memory and addressing circuitry which carries an input address to the memory. However, the voltage levels of the input address are often low bipolar voltage levels, such as are used in TTL, rather than the high voltage levels which are used by the MOS memory logic. These low voltages can be further degraded in value as the input address signal is gated into the buffer. For example, typical low and high TTL logic signals are 0.8 volts and 2.1 volts, respectively. A typical buffer circuit uses NMOS transistors which have a high threshold of approximately 2.0 volts. When the TTL logic high signal of 2.1 volts is gated across an input transistor in the buffer, it is conceivable that the resulting voltage will degrade to less than 2.0 volts. Therefore, should this input be now applied to the latch, it would be insufficient to turn ON an NMOS transistor therein, and the latch would not store the proper input value.
The prior art has provided a number of techniques to overcome this problem such as capacitive boosting of the low bipolar voltage levels. One such circuit is described in U.S. Pat. No. 4,038,567 to Lewis et al. In this circuit, the input voltage is boosted by a capacitor to ensure that the NMOS transistors are properly latched. However, even though this type of circuit has proven efficient, it still requires that the input signal be passed through an NMOS input transistor before being latched. The need for this extra transistor increases the cost of the buffer since associated timing circuitry is required for control thereof. Moreover, the boosting capacitors use up a finite area of the microchip, thus decreasing the size of the memory that can be fabricated thereon.